Rtos support str912using binary semaphore between 2 tasks
This is a continuation of co-pending application Ser. This invention relates to digital computers, and particularly to digital computers adapted for use in a distributed data processing system comprising and sharing load among a plurality of individual digital computers. Digital computers in general are well known in the prior art.
Digital computers have been employed in "distributed computing networks" in which a plurality of computers are interconnected and are programmed to cooperate on an overall data processing task involving a related body of data and a related body of tasks to be performed thereon, with some computers doing some of the processing and then passing results or status information to other of the computers which perform other of the processing.
Using traditional general purpose computers in distributed computing networks has required that each computer perform a portion of the networking functions intercommunication, coordination, priority arbitration, etc.
The computers of the present invention overcome the overhead-prone drawbacks of the prior art by providing an architecture in which additional intelligence is provided at junction points of the computer network, this intelligence being sufficient to perform the networking overhead functions.
Flow of data and status information around the rtos support str912using binary semaphore between 2 tasks is thus expedited, and the CPU of each computer is freed to devote its attention to direct data processing tasks. An intelligent controller is provided ahead of the video RAMs to free the CPU of detailed bitmap manipulation in support of graphic dislays.
It is a particular object of the present invention to provide digital computers that may be interconnected to form a highly efficient distributed computing system. Additional objects and advantages will be apparent to one skilled in the art, after referring to the description of the preferred embodiment and the appended drawings. For clarity, the figure numbers are based on the number of the section referring to the figure.
For example, figures first referred to in Section 1 are numbered in the "" series, figures first referred to in Section 2 in the "" series, and so on. CPU is connected to memory by memory busand must control all transfers over memory bus System console connects directly into CPUwhich must control all transfers to system console The controllers, and may be provided with some limited intelligence to control low-level details of transfers effected through them, but CPU must provide all high-level control, setting up the controllers and overseeing returns of status information from them.
Video RAMs may be provided to contain "bit maps" of screen information for user terminals. CPU provides bit map data and stores it in the RAMs in a form in which it may be displayed on user terminals.
Communication between computers of the present invention configured as a distributed system, is effected by memory references. All memory locations within the distributed system are accessible to any CPU--a CPU may read from a write to a memory location associated with another CPU on the distributed system with the same facility with which it may access any of the memory locations associated with itself.
All memory access requests from a CPU are passed over LMB bus to MCUwhich determines from the memory address whether the desired location is associated with the local computer the computer containing the CPU and MCU or one of the other computers comprising the network. If the latter, MCU passes the request over I-Bus whence the MCU 's of all other computers on the system examine the memory address; the computer having that address within its local memory performs the memory access, the data being passed over I-Bus between the MCU of the computer having the memory address and the MCU of the requesting computer.
This feature referring briefly to FIG. An arbitration scheme is provided to ensure that no computer can monopolize the I-Bus and that no computer can be deprived of the use of the I-Bus. This scheme is based on a rotating priority, wherein the computer that has just used the bus is given lowest priority and must wait till other requesting computers have used the bus before it can use the bus again.
System Console is grouped with other user terminals, and is does not occupy the special role it had in prior-art machines. References to memory locations of another computer of the distributed computer network are "passed through" MCU to I-Bus An operating system not shown on FIG. In summary, the computer of the present invention is well suited to distributed processing applications, from two standpoints: Each board contains its own LMB Bus which does not leave the board.
Each board has a connection to I-Bus Each board has a Memory Bus which may leave the board and connect to optional expansion memory and video memory boards; up to 2 MBytes of memory may be accommodated on the computer board and are connected to Memory Bus ; additional memory and video memory boards may be connected to the computer board's Memory Bus to expand each computer's memory capacity.
Up to sixteen such computers each with associated memory and video memory boards may rtos support str912using binary semaphore between 2 tasks accommodated in a single cabinet, the cabinet including a "backplane" comprising sockets into which all the boards are plugged, and permanent wiring interconnecting the sockets. I-Bus is made up of backplane wiring and interconnects all the computers plugged into the cabinet to form a distributed computer network.
The sixteen computers may share a total memory space of MBytes. As described above, any of the computers may access any location of the MBytes, which may thus be regarded as a "global address space".
It is controlled by a 64 bit microinstruction and uses pipelining techniques for enhanced performance. All data paths, registers and standard accumulators are 32 bits wide, while the FPU registers and functional units are a full 64 bits wide.
These buses connect the four major subsections of the computer: All memory requests are directed through LMB to MCU where the request is either granted locally if the memory locations are in the local spaceor are redirected to the global memory bus an I-Bus request. These are non-architectural buses; that is, they support internal, underlying functions and do not directly bear upon the execution of any user-invoked functions.
The XD is a bi-directional data path which multiplexes its 16 bits onto and off of the 64 bit uWord bus. Most operations are completed in a ns cycle with the remainder of operations requiring ns.
It is implemented in a pin PGA package. Rtos support str912using binary semaphore between 2 tasks chip fits into a small 64 pin PGA package.
Clock Generation--a multiphased clock based on 80 ns basic system clock which generates a ns microcycle.
A microprogrammable stretch to ns is used for longer operations. This interface also includes hardware controlled referenced and modified bits which support rtos support str912using binary semaphore between 2 tasks to 16 MBytes of local memory without microcode support.
The Memory portion of the board contains the main memory control unit MCU and 2 Megabytes of main memory itself. The MBus is also the connection for bit mapped video rtos support str912using binary semaphore between 2 tasks that are attached to the main memory address space see section 5.
The Memory portion is entirely controlled by two gate arrays: Since the formats and protocols on rtos support str912using binary semaphore between 2 tasks various buses are contrived to facilitate passing from one to the other, these two gate arrays are basically rtos support str912using binary semaphore between 2 tasks directors and error checking devices which control all the interactions that take place among the LMB, and I-Bus and the MBus.
The LMB initiates all local memory accesses while the I-Bus initiates all accesses of this particular node from other global nodes. The MBus is essentially an internal bus to this memory portion which carries the actual address and data of the local RAM's themselves. This bus is "raw", unaligned, uncorrected data which is stored in the RAMs themselves. This MBus has expansion capability so that up to 16 Mbytes can be addressed by this MCU the two gate arrays without adding more control.
Thus, the MBus goes off-board so that additional memory can be added either in the form of standard DRAMs or in the form of memory mapped graphics. To illustrate the flow of a memory access, consider a CPU reference. Rtos support str912using binary semaphore between 2 tasks then makes a determination of whether the reference was a local reference--i.
Either the memory array on the board itself 2 Mbytes or an external expansion memory on the MBus will respond with the data. If the data required aligning or correcting, the MCU would have taken the data into the gate arrays themselves, manipulated it as required, and rebroadcast the data back onto the LMB prior to signaling the computer. Had the reference been global--i. The memory portion of a computer board is designed around MCU which comprises two gate arrays:.
Its main functions include: Error Detection and correction circuitry correct all single bit errors and any double bit errors that contain at least one hard bit failure ; Refresh and Sniff control; Read-Modify-Write control; data alignment; interrupt and special function control. This primary MCU control chip is necessary for high speed response to memory requests. Rtos support str912using binary semaphore between 2 tasks major functions of this array is: The Memory Data Bus is the common data path for transmitting data to and from all system memories including the 2 Megabytes that can be on-board and VRAMs This is a specified bus interface which is recognized by the MCU and is described in detail in section 3.
This I-Bus is a global memory bus which connects computer nodes via a common memory space. Section 2 describes this bus in detail. The 32 bit data words and rtos support str912using binary semaphore between 2 tasks ERCC bits implement a portion of the memory address space. It is two way interleaved to enhance consecutive access performance.
Additional off-board memory may be connected to MBus ; this may additional main memoryor VRAMs for storing screen bit maps see section 5. This subsystem, run by a microprocessor, is the only intelligent part of the board upon power-up. Its SCP functions include: The microprocessor controls the power up sequence by holding the CPU portion and Memory portion of the board in Reset state.
Using microprocessor firmware stored in the power up PROMsit does a self-check, verifying enough of this section to read more microprocessor firmware off of a disk into the ucomputer RAM Memory. Any failure to this point will be displayed on the front panel LED which is under control of the Once the uP Memory is loaded with a full complement of firmware, a more complete power-up diagnostic is run, including the MIP gate array selftest pin see CPU sectionother CPU testing, memory testing and video display indications.
It then finishes the power up diagnostic testing and starts the CPU. During normal run time, IOC services devices connected to it. All communication with CPU takes place through buffer The microprocessor does the interpreting, scheduling and device control of these requests in parallel to normal CPU execution.
Data for output are likewise placed by CPU into buffer The microprocessor features include: The will be run at 8 MHz in order to maximize its performance. This is a 32 KByte shared memory area. The remainder of the space is used for data buffering to insure high bandwidth burst data movement support. Data is packed into the buffer in DG format.
For communication to main memory, this section provides a direct memory access state machine which does not require firmware control. Each memory access is either a double word 32 bits read or double word write. This interface will support a transfer rate of 7. Rtos support str912using binary semaphore between 2 tasks of data are loaded into or read from that buffer by the CPU which then signals the via an interrupt line.
The then processes that data block in an appropriate manner specified by the data block itselfand, in turn, the will signal the acceptance or rtos support str912using binary semaphore between 2 tasks of that block via a dedicated signal to the CPU which causes a micro level trap microcode visible but not macrocode visible.
Support is provided for two 5. The target drives record data rtos support str912using binary semaphore between 2 tasks 96 TPI and have a This bus is 8 bits wide plus parity and transfers data at a an Asynchronous rate of 1.
Drivers and receivers are single-ended. This communications protocol is rated at 10 MBit per second utilizing coaxial cable.